1 ? fn7455.3 preliminary el8186 micropower single s upply rail-to-rail input-output op amp the el8186 is a micropower operational amplifier optimized for single supply operation at 5v and can operate down to 2.4v. the el8186 draws minimal supply current while meeting excellent dc-accuracy noise and output drive specifications. competing devices seriously degrade these parameters to achieve micropower supply current. offset current, voltage and current noise, slew rate, and gain-bandwidth product are all two to ten times better than on previous micropower op amps. the el8186 can be operated from one lithium cell or two ni-cd batteries. the input range includes both positive and negative rail. the output swings to both rails. features ? 55a supply current ? 400v typical offset voltage ? 500pa input bias current ? 400khz gain-bandwidth product ? 1mhz -3db bandwidth ? 0.13v/s slew rate ? single supply operation down to 2.4v ? rail-to-rail input and output ? output sources and si nks 26ma load current applications ? battery- or solar-powered systems ? 4ma to 25ma current loops ? handheld consumer products ? medical devices ? thermocouple amplifiers ? photodiode pre amps ? ph probe amplifiers pinouts el8186 (6-pin sot-23) top view el8186 (8-pin so) top view ordering information part number package tape & reel pkg. dwg. # el8186iw-t7 6-pin sot-23 7? (3k pcs) mdp0038 el8186iw-t7a 6-pin sot-23 7? (250 pcs) mdp0038 el8186is 8-pin so - mdp0027 EL8186IS-T7 8-pin so 7? mdp0027 el8186is-t13 8-pin so 13? mdp0027 1 2 3 6 4 5 +- out vs- in+ vs+ enable in- 1 2 3 4 8 7 6 5 - + nc in- in+ enable vs+ vout vs- nc data sheet june 14, 2005 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-352-6832 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2004, 2005. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn7455.3 june 14, 2005 absolute maxi mum ratings (t a = 25c) supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5v differential input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v s + 0.5v output short-circuit duration . . . . . . . . . . . . . . . . . . . . . . .indefinite ambient operating temperature range . . . . . . . . . .-40c to +85c storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v s = 5v, 0v, v cm = 0.1v, v o = 1.4v, t a = 25c unless otherwise specified. parameter description conditions min typ max unit v os input offset voltage 0.4 1 mv long term input offset voltage stability tbd v/mo input offset drift vs temperature 1 v/c i os input offset current 0.4 2 na i b input bias current 0.5 3 na e n input noise voltage density f o = 1khz 25 nv/ hz i n input noise current density f o = 1khz 0.1 pa/ hz cmir input voltage range guaranteed by cmrr test 0 5 v cmrr common-mode rejection ratio v cm = 0v to 5v 90 110 db psrr power supply rejection ratio v s = 2.4v to 5v 90 110 db a vol large signal voltage gain v o = 0.5v to 4.5v, r l = 100k ? 200 500 v/mv v o = 0.5v to 4.5v, r l = 1k ? 25 v/mv v out maximum output voltage swing output low, r l = 100k ? 36mv output low, r l = 1k ? 130 200 mv output high, r l = 100k ? 4.994 4.997 v output high, r l = 1k ? 4.8 4.88 v sr slew rate 0.09 0.13 0.17 v/s gbw gain bandwidth product f o = 100khz 400 khz bw -3db bandwidth unity gain, c load = 27pf, r f = 100 1 mhz i s,on supply current, enabled 40 55 75 a i s,off supply current, disabled 310a i o + short circuit output current r l = 10 ? 18 31 ma i o - short circuit output current r l = 10 ? 17 26 ma v s minimum supply voltage 2.2 2.4 v v inh enable pin high level 2v v inl enable pin low level 0.8 v i enh enable pin input current v en = 5v 0.25 0.7 2 a i enl enable pin input current v en = 0v -0.5 0 +0.5 a ? v os ? time ------------------ ? v os ? t --------------- - el8186
3 fn7455.3 june 14, 2005 typical performance curves figure 1. unity gain frequency response vs supply voltage figure 2. frequency response vs supply voltage figure 3. supply current vs supply voltage figur e 4. input offset voltage vs output voltage figure 5. input offset voltage vs common-mode input voltage figure 6. input bias + offset currents vs common- mode input voltage -6 -3 0 3 6 1k 10k 100k 1m 10m frequency (hz) gain (db) v s =2.5v -9 a v =1 c l =27pf r f =100 ? r g =open v s =1.25v v s =1.0v a v =100 r l =10k ? c l =2.7pf r f /r g =99.02 r f =221k ? r g =2.23k ? 0 gain (db) 15 20 25 40 45 30 35 5 10 100 10k 100k 1m frequency (hz) 1k v s =1.0v v s =1.25v v s =2.5v 23.545.5 supply voltage (v) 2.5 5 4.5 3 0 supply current (a) 20 50 60 30 40 10 -200 input offset voltage (v) -100 0 150 200 50 100 05 output voltage (v) 13 24 v dd =2.5v v dd =5v v cm =v dd /2 a v =-1 -150 -50 -100 input offset voltage (v) -80 -20 0 -60 -40 05 common-mode input voltage (v) 13 24 v os , v 1 input bias, offset currents (pa) 1k 10k 10 100 05 common-mode input voltage (v) 13 24 i b + i os i b - el8186
4 fn7455.3 june 14, 2005 figure 7. a vol vs frequency @ 1k ? load figure 8. a vol vs frequency @ 100k ? load figure 9. psrr vs frequency f igure 10. cmrr vs frequency figure 11. voltage noise vs frequency fi gure 12. current noise vs frequency typical performance curves (continued) -20 gain (db) 0 20 80 100 40 60 10 10k 1m frequency (hz) 100 -150 phase () 200 150 100 50 0 -50 -100 100k 1k phase gain -80 gain (db) 40 120 80 -40 0 1 1k 100k 10m frequency (hz) 10 -120 phase () 80 40 0 -40 -80 10k 1m 100 0 10 20 30 40 50 60 70 80 90 100 110 120 1 10 100 1k 10k 100k 1m frequency (hz) psrr (db) psrr+ psrr- 0 10 20 30 40 50 60 70 80 90 100 110 120 1 10 100 1k 10k 100k 1m frequency (hz) cmrr (db) 1k 100 10 1 10 100 1k 10k 100k voltage noise (nv/ hz) frequency (hz) 0.01 0.10 1.00 10.00 1 100 10k 100k frequency (hz) current noise (pa/ hz) 10 1k el8186
5 fn7455.3 june 14, 2005 figure 13. v os vs temperature figure 14. psrr vs temperature figure 15. cmrr vs temperature figure 16. a vol vs temperature figure 17. i b vs temperature figure 18. i s vs temperature typical performance curves (continued) -500 -400 -300 -200 -100 0 100 200 300 400 500 -50 0 50 100 temperature (c) input offset voltage (v) sot23-6 package 10 samples 90 95 100 105 110 115 120 125 130 -50 0 50 100 temperature (c) psrr (db) sot23-6 package 90 95 100 105 110 115 120 -60 -40 -20 0 20 40 60 80 100 temperature (c) cmrr (db) sot23-6 package 100 105 110 115 120 125 130 -60 -40 -20 0 20 40 60 80 100 temperature (c) open loop gain (db) sot23-6 package -1500 -1000 -500 0 500 1000 1500 2000 -60 -40 -20 0 20 40 60 80 100 temperature (c) i b (pa) sot23-6 package 30 35 40 45 50 55 60 65 70 -60 -40 -20 0 20 40 60 80 100 temperature (c) i s (ma) sot23-6 package el8186
6 fn7455.3 june 14, 2005 figure 19. package power dissipation vs ambient temperature figure 20. package power dissipation vs ambient temperature typical performance curves (continued) jedec jesd51-7 high effective thermal conductivity test board 0 power dissipation (w) 0.4 1 0.8 0.2 0.6 0 100 125 150 ambient temperature (c) 50 25 75 85 435mw 909mw j a = 2 3 0 c / w s o t 2 3 - 6 j a = 1 1 0 c / w s o 8 jedec jesd51-3 low effective thermal conductivity test board 0 power dissipation (w) 0.2 0.7 0.6 0.1 0.4 0.5 0.3 0 100 125 150 ambient temperature (c) 50 25 75 85 391mw 625mw j a = 1 6 0 c / w s o 8 j a = 2 5 6 c / w s o t 2 3 - 6 el8186
7 fn7455.3 june 14, 2005 applications information introduction the el8186 is a rail-to-rail input and output micro-power single supply operational ampl ifier with an enable feature. the device achieves rail-to-ra il input and output operation and eliminates the concerns introduced by a conventional rail-to-rail input and output operational amplifier. rail-to-rail input the input common-mode voltage range of the el8186 goes from negative supply to positi ve supply without introducing offset errors or degrading performance associated with a conventional rail-to-rail input operational amplifier. many rail- to-rail input stages use two differential input pairs, a long-tail pnp (or pfet) and an npn (or nfet). severe penalties have to be paid for this topology. as the input signal moves from one supply rail to another, the operational amplifier switches from one input pair to the other causing drastic changes in input offset voltage and an undesired change in magnitude and polarity of input offset current. the el8186 achieves input rail-to-rail performance without sacrificing important precision specifications and without degrading distortion performance. the el8186's input offset voltage exhibits a smooth behavior throughout the entire common-mode input range. the input bias current versus the common-mode voltage range for the el8186 gives consistent behavior from typically 10mv above the negative rail all the way up to the positive rail. input bias curre nt compensation the input bias currents of the el8186 are reduced to a typical 500pa while maintaining excellent bandwidth for a micro-power operational amplif ier. inside the el8186 is an input bias cancelling circuit. the input stage transistors are still biased with an adequate amount of current for speed but the cancelling circuit sinks most of the base current, leaving a small fraction as input bias current. the input bias current compensation/cancellation operates from typically 10mv above the negative rail to the positive supply rail. rail-to-rail output a pair of complementary mosfet devices achieves rail-to- rail output swing. the nmos sinks current to swing the output in the negative directio n. the pmos sources current to swing the output in the posi tive direction. the el8186 with a 100k ? load will swing to within 3mv of the supply rails. enable/disable feature the el8186 offers an en pin. the active low enable pin disables the device when pulled up to at least 2.2v. upon disable the part consumes typi cally 3a, while the output is in a high impedance state. the en also has an internal pull down. if left open, the en pin will pull to negative rail and the device will be enabled by default. the high impedance at output during disable allows multiple el8186s to be connected together as a mux. the outputs are tied together in parallel and a channel can be selected by the en pin. typical applications figure 21. thermocouple amplifier thermocouples are the most popular temperature-sensing device because of their low cost, interchangeability, and ability to measure a wide range of temperatures. the el8186 is used to convert the differential thermocouple voltage into single-ended signal with 10x gain. the el8186's rail-to-rail input characteristic allows the thermocouple to be biased at ground and the converter to run from a single 5v supply. - + 5v + v+ v- el8186 k type thermocouple 10k ? r 3 10k ? r 2 r 4 100k ? r 1 100k ? 410v/c el8186
8 fn7455.3 june 14, 2005 so package outline drawing el8186
9 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7455.3 june 14, 2005 sot-23 package outline drawing note: the package drawing shown here may not be the latest version. to check the latest revision, please refer to the intersil w ebsite at http://www.intersil.com/design/packages/index.asp el8186
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